1. Field of the Invention
This invention relates to random access memory arrays and more particularly to a high performance static multi-bit random access memory arrays.
2. Brief Description of the Related Technology
Random access memory (RAM) arrays are employed within a variety of digital systems to provide data storage. A static RAM stores bits in an array of flip-flops, whereas a dynamic RAM stores bits as charged capacitors. A bit once written in a static RAM stays there until rewritten, unless the power is turned off. In a dynamic RAM, the data will disappear due to discharge, unless "refresh".
A typical static RAM circuit includes an array of RAM cells in a predetermined arrangement of columns and rows. Upon each cycle a row is enabled to allow the reading of a selected cell through a differential sense amplifier. RAM arrays have been used extensively as cache in high performance microprocessors. Caches are small and fast memories that are either included on the same monolithic chip with the microprocessor core, or are coupled nearby. With advancement in technology, the cache size increases 50 to 100 folds over the last 10 years. RAM arrays take a large area and become major contributor to power dissipation.
To reduce the power dissipation, the cache array is divided into sets with a single set enabled per access. A subset of index bits from the requested address is used to select and enabled only a single set. Each set of the cache array has its own address decoders, input buffers, sense amplifiers, and routing buses. This organization of cache array trades area for power dissipation. Furthermore, the routing of the buses from multiple sets of cache array introduces extra delay in cache access time.
In addition, the transistor's size and delay scales better with technology in comparison to interconnect, metal routing. The shrinking geometry of transistor's size makes it difficult to efficiently lay out the random-access memory (RAM) cell and associated address decoder cell and sense amplifier without violating design rules. In term of interconnect, each RAM cell required a total of five metal lines; one row line, two bit lines, and two power lines. Only the power lines can be shared with the neighbor cells. The RAM cells is dominated by interconnects and the speed is limited by the resistance-capacitance delay of the interconnects.